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february 2012 doc id 17553 rev 2 1/29 AN3223 application note driver for double flash led with i2c interface introduction this application note is dedicated to the design of a flash led driver using the stcf04 device, which is a buck-boost converter with an i2c interface dedicated to charging a super- capacitor. the schematic, functional description, recommendations for pcb layout, and external component selection are also covered. this device is designed for driving four leds. a detailed functional description can be found in figure 1 below. figure 1. picture of the demonstration board and the external transistor with tdk edlc am05038v1 www.st.com
contents AN3223 2/29 doc id 17553 rev 2 contents 1 schematic description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 application schematic with external transistor . . . . . . . . . . . . . . . . . . . . . . 4 2 selection of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 input and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 led selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 ntc and rx resistor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pcb design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pcb design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2.1 an example of the 3-layer pcb with the external transistor stl8nh3ll 7 4 internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 accessing the internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 ntc feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 torch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.6 flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 the status register and the atn pin . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 ready pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 function of the ready pin in monitoring mode and torch mode (fixed) . 18 7.2 function of the ready pin in flash mode . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3 function of the ready pin in torch mode (optimized) . . . . . . . . . . . . . . 19 8 the light sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AN3223 contents doc id 17553 rev 2 3/29 9 reading and writing to the stcf04 registers through the i2c bus . . . 22 9.1 writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2 writing to multiple registers with incremental addressing . . . . . . . . . . . . 22 9.3 reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.4 reading from multiple registers with incremental addressing . . . . . . . . . 23 10 examples of register setup for each mode . . . . . . . . . . . . . . . . . . . . . . 25 10.1 example 1: 10 a flash with 30 ms duration . . . . . . . . . . . . . . . . . . . . . 25 10.2 example 2: 60 ma torch with 10 s duration . . . . . . . . . . . . . . . . . . . . . . . 25 10.3 example 3: an auxiliary led running at 10 ma for 500 ms . . . . . . . . . . . 26 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
schematic description AN3223 4/29 doc id 17553 rev 2 1 schematic description the flash led driver stcf04 has a high operational frequency (1.8 mhz) which allows the use of small-sized external components. 1.1 application schematic with external transistor **: connect to v i , gnd, sda, or scl to choose one of the four different i2c slave addresses. blue rectangle: optional components to support auxiliary functions. figure 2. typical application schematic am05040v1
AN3223 selection of external components doc id 17553 rev 2 5/29 2 selection of external components 2.1 input and output capacitor selection it is recommended to use ceramic capacitors with low esr as input and output capacitors. it is recommended to use 10 f / 6.3 v as a minimum value for the input capacitor, and 10 f / 6.3 v as the optimal value for the output capacitor to achieve a good stability of the device, for a supply range varying from low input voltage (2.5 v) to the maximum ratings of output power. note: see recommended components in ta b l e 1 . 2.2 inductor selection the stcf04 device works with the switching algorithm ilim-zcom. it charges the inductor until the current crosses the threshold for the ilim function and then it discharges the energy in the inductor to the output until it reaches the zero current value. therefore, it is recommended to use a 1 h inductor as the minimum value, which guarantees a proper function with the used algorithm and speed of used components in the silicon design. note: see recommended components in ta b l e 1 . 2.3 led selection all leds with a forward voltage range from 2.5 v to 4.5 v are compatible with the stcf04. the forward voltage spread of any selected led must, however, lay within this range (2.5 v to 4.5 v). it is possible to set the level of the led current in flash mode and torch mode by setting the dimming registers. the maximum level of the led current in flash mode can be set by changing the external flash resistor. note: see recommended components in ta b l e 1 . 2.4 ntc and rx resistor selection the stcf04 requires a negative thermistor (ntc) for sensing the led temperature, as well as an r x resistor and an external voltage reference in order to use the ntc feature. please refer to the typical application schematic in figure 2 for more details. once the ntc feature is activated, the internal switch connects the r x resistor to the ntc, and this creates a voltage divider supplied by the external reference voltage connected to the ntc. if the temperature of the ntc-thermistor rises due to the heat dissipated by the led, the voltage on the ntc pin increases. when this voltage exceeds 0.56 v, the ntc_w bit in the status register is set to high, and the atn pin is set to low to inform the microcontroller that the led is becoming hot. the ntc_w bit is cleared by reading the status register. if the voltage on the ntc pin rises further and exceeds 1.2 v, the ntc_h bit in the status register is set to high, and the atn pin is set to low to inform the microcontroller that the led is too hot and the device automatically goes to ready mode to avoid damaging the led.
selection of external components AN3223 6/29 doc id 17553 rev 2 this status is latched, until the microcontroller reads the status register. reading the status register clears the ntc_h bit. the selection of the ntc and rx resistor values strongly depends on the power dissipated by the led and all components surrounding the ntc-thermistor and on the cooling capabilities of each specific application. the rx and the ntc values in ta b l e 1 below work well in the demonstration board presented in this application note. a real application may require a different type of ntc-thermistor to achieve optimal thermal protection. the procedure to activate the ntc-feature is described in section 5.2: monitoring mode . table 1. recommended components component manufacturer part number value size l murata lqm2hpn1r0mjc 1 h / 1.5 a 2.5 x 2.0 x 1.1 mm tdk vls252012t-1r0n1r7 1 h / 1.7 a 2.5 x 2.0 x 1.2 mm cin,cout tdk c1608x5r0j106mt 10 f / 6.3 v 0603 rx rohm mcr01mzpj15k 15 k 0402 ntc murata ncp21wf104j03ra 100 k 0805 csup murata dme2w5r5k404m 400 mf / 5.5 v 20.5 x 18.5 x 3 mm tdk edlc152344 550 mf / 5.5 v 44 x 23 x 1.5 mm edlc272020 500 mf / 5.5 v 20 x 20 x 2.7 mm cap-xx gs 2 19f 1.6 f / 5 v 40 x 17 mm led modul luxeon 4x lxcl-pwf4 white led 0805 t fl stmicroelectronics stl8nh3ll 8 a / 12 m 3.3 x 3.3 x 0.9 mm r fl tyco tl2br01fte 0r01 1206 c int (1) tdk 10 f / 6.3 v 0402 r light (1) tyco 0402 t foto (1) vishay temt6000 4 x 2 x 1 mm auxled red led 0603 c r 100 nf 0402 1. optional components for the auxiliary light sensor feature.
AN3223 pcb design doc id 17553 rev 2 7/29 3 pcb design 3.1 pcb design rules the stcf04 is a powerful switching device working from low input voltages and high duty cycle, where the pcb must be designed in line with switched supplies design rules. the power tracks (or wires on the demonstration board) must be as short as possible and wide enough, because of the large currents involved. it is recommended to use a 3 to 4-layer pcb to obtain the best performance. all external components must be placed as close as possible to the stcf04. all high-energy switched loops should be as small as possible to reduce emi. most of the leds need efficient cooling, which may be done by using a dedicated copper area on the pcb. please report to the selected led's reference guide to design the heatsink. if a modification to any pcb layer is required, it is highly recommended to use an adequate number of vias. place the ntc resistor as close as possible to the led for good temperature sensing. direct connection between gnd and pgnd is necessary in order to achieve correct output current value. no led current should flow through this track! vias connecting the stcf04 pins to the copper tracks (if used) must be 0.1 mm in diameter for the bga version. it is recommended to connect the leds close to the v out and iled pins for a stable operation margin. the impedance of this connection should be lower than 0.4 . 3.2 pcb layout 3.2.1 an example of the 3-layer pcb with the external transistor stl8nh3ll figure 3. top layer am05042v1
pcb design AN3223 8/29 doc id 17553 rev 2 figure 4. middle layer 1 figure 5. bottom layer am0504 3 v1 s upercap lead s ? bottom s ide am05044v1
AN3223 pcb design doc id 17553 rev 2 9/29 figure 6. top overlay addre ss s election - vbat - gnd - s da - s cl ( us e zero ohm re s i s tor for the s etting) am05045v1
internal registers AN3223 10/29 doc id 17553 rev 2 4 internal registers 4.1 accessing the internal registers there are six internal registers in the stcf04 (which are the command, flash, aux_led, status, feature, and torch registers). the status register is read-only. the command and feature registers can be accessed in any operation mode. all the other registers can be accessed in any mode, except in shutdown, shutdown + ntc, and monitoring mode. when the device enters shutdown mode, the flash, aux_led, status, and torch registers are cleared. t he command and feature register values remain untouched when entering shutdown mode, however reading their value gives 0 when the bit pwr_on = 0. ta b l e 2 shows the accessibility of each register in all operation modes. in other words, whenever the pwr_on bit in the command register is set to zero, then only the command and feature registers can be accessed. it is necessary to set the pwr_on bit to 1 to access all the registers. table 2. accessibility of internal registers register address mode shutdown value power-on reset value shutdown and monitoring idle, charging, flash, torch and aux led command 00 read / write read / write untouched cleared flash 01 inaccessible read / write cleared cleared aux_led 02 inaccessible read / write cleared cleared status 03 inaccessible read only cleared cleared feature 04 read / write read / write untouched cleared torch 05 inaccessible read / write cleared cleared
AN3223 operation modes doc id 17553 rev 2 11/29 5 operation modes 5.1 shutdown mode shutdown mode is entered after the power-on reset. this mode is mainly used to decrease the power consumption of the device. in this mode, only the i 2 c interface is live. the only action which can be performed in shutdown mode is to access the command and feature registers. entering shutdown mode by writing to the command register aborts any running operation and clears the values of the flash, aux_led, status, and torch registers. the command and feature register values are not affected by entering shutdown mode, but an attempt to read their value always gives 0 when the bit pwr_on = 0. the following data must be written to the command register to enter shutdown mode. 5.2 monitoring mode the super-capacitor voltage is monitored by a comparator in this mode. the comparator is the only analog circuit which is enabled and that is why the consumption of the stcf04 is minimized in this mode. information about the super-capacitor voltage is given by the logic level on the ready pin. if the voltage is higher than v dcthreshold , the ready pin is low. when the voltage falls by 200 mv below the v dcthreshold , the ready pin goes high. the level of the v dcthreshold can be set by the vdc_0 and vdc_1 bits in the feature register. monitoring mode can be entered from shutdown mode by setting the montr bit in the command register to 1. table 3. command register data for entering shutdown mode cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 0 x xxxx00 msb lsb table 4. v dcthreshold voltage setup vdc_1 vdc_0 v dcthreshold 00 4.5 v 01 5.0 v 10 5.5 v table 5. command register data for entering monitoring mode cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 0 x xxxx10 msb lsb
operation modes AN3223 12/29 doc id 17553 rev 2 note: monitoring mode can be also entered from idle mode, but the device has a greater power consumption in this case. 5.3 idle mode idle mode allows accessing of all the internal registers. the ntc feature can be activated in this mode and the temperature of the led can be sensed by the a/d converter of the microcontroller. the following data must be written to the command register to enter idle mode. 5.4 ntc feature the ntc feature can be used in all modes. the ntc is activated automatically in the flash and torch mode regardless of the value of the ntc_on bit. ntc must be activated manually in all the other modes. the ntc feature is activated by setting the ntc_on bit in the command register to 1. as soon as the ntc feature is activated, the internal switch connects the ntc resistor to the r x resistor, thereby creating a voltage divider. the voltage on this divider can be, if desired, monitored by the a/d converter of the microcontroller. an external voltage reference must be connected to the ntc to use this feature. the bits ntc_w and ntc_h of the status register are not properly set if there is no external reference voltage connected to the ntc. if the ntc feature is not going to be used, neither the negative thermistor nor the external reference needs to be connected. in this case, it is recommended to ground the rx pin. as the ntc feature is automatically activated during flash and torch mode, leaving the rx pin floating could lead to unwanted interruptions of the light due to non-defined voltage on the rx pin. if the ntc feature is activated and the pwr_on bit in the command register is zero, the bits ntc_w and ntc_h in the status register are not set properly, because the comparators which determine their values are not enabled in this case. but it is still possible to measure the voltage on the ntc pin through the a/d converter. ta b l e 8 summarizes the ntc feature possibilities. table 6. command register data for entering idle mode cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 100xx000 msb lsb table 7. command register data for activation of the ntc feature cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a xxx1xxx0 msb lsb
AN3223 operation modes doc id 17553 rev 2 13/29 5.5 torch mode this mode is intended to be used for low light intensities. the led current in torch mode can be adjusted in a range from 15 ma up to 320 ma. torch mode is activated by writing the following data to the command register. the torch dimming register value (tdim) must also be set, unless it has already been set during a previous operation. if the tdim register is not set, then the default output current value is at the minimum. it is also possible to set the safety timeout for torch mode through the ttrch1 and ttrch0 bits. if torch mode was terminated by entering ready or flash mode, it can be restarted again by writing the corresponding data to the command register only, because entering any of the ready and flash modes does not influence the tdim value. if the torch mode was terminated by entering shutdown mode, then the tdim value must be set again during restart of torch mode, because entering shutdown mode clears the tdim and ttrch values. as soon as torch mode is activated, the ntc feature is automatically activated too in order to protect the led against overheating. the ntc feature is activated even if the ntc_on bit in the command register is set to zero. 5.6 flash mode this mode is intended to be used for high light intensities. the led current in flash mode can be adjusted up to 12 a with the input voltage ranging from 2.7 v up to 5.5 v with recommended external components. table 8. ntc feature possibilities operation mode way of activation voltage on the rx-ntc divider ntc_w, ntc_h bits shutdown manual available not set monitoring manual available not set idle manual available set charging manual available set flash automatic available set torch automatic available set aux led manual available set table 9. command register data for entering torch mode cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 1 0 1xxxx0 msb lsb
operation modes AN3223 14/29 doc id 17553 rev 2 the flash register value must also be set. the activation of flash mode requires the flash pin to be high. flash mode is active only when the flash_on bit in the command register is set to 1 and the flash pin is high. this gives the user the possibility to choose between a soft and a hard triggering of the flash mode. soft triggering is done by writing data to the internal registers only, while the flash pin is permanently kept high, e.g. by connecting it to v bat . this saves one pin of the microcontroller, which can be used for a different purpose, but this way of triggering is less accurate than the hard one. the second disadvantage of this solution is that the flash duration can only be set in discrete steps of the internal timer. hard triggering of the flash mode requires the microcontroller to manage the flash pin. the command and the flash registers are loaded with data before the flash pin is set to high. this allows the user to avoid the i2c bus latency. flash mode then starts as soon as the flash pin is set to high. it takes typically about 0.3 ms to ramp up the led current to the adjusted value. when the flash pin is kept high long enough, the internal timer reaches zero and the flash mode is over. as soon as the flash is timed out, the atn pin is pulled down for 11 s to inform the microcontroller that the status register was updated and that the flash is over. if the flash pin is set to low before the internal timer reaches zero, flash mode is interrupted and can be restarted by setting the flash pin to high again. the internal timer is stopped while the flash pin is low. this means that the user can split the flash into several pulses of a total length equal to the ftim value. figure 7 shows the case for ftim = 17 (130 ms flash time). the cumulative time when the flash pin is high is 150 ms (5 pulses 30 ms long), but the last flash pulse is only 10 ms long. the reason is that the internal flash timer reaches zero and the flash_on bit is set to 0. table 10. command register data for entering flash mode cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 1 1 0xxxx0 msb lsb
AN3223 operation modes doc id 17553 rev 2 15/29 hard triggering therefore allows a smooth setting of the flash duration. the resolution is about 8.8 s. the minimum flash duration is limited by the ramp-up time of the led current and the maximum is limited by the ftim value. note: when performing multiple flashes, it is necessary to make sure that the super-capacitor contains enough energy to cover all the required flashes in the burst. if the super-capacitor voltage falls below 4.2 v during the burst, the internal flash timer is stopped and the device waits until the super-capacitor is recharged to the v dcthreshold value. then the burst can continue. see figure 8 for more details. figure 7. splitting the flash pulse into several shorter pulses am07 8 01v1
operation modes AN3223 16/29 doc id 17553 rev 2 figure 8. burst of flashes with insufficient energy in the super-capacitor am07 8 02v1
AN3223 the status register and the atn pin doc id 17553 rev 2 17/29 6 the status register and the atn pin a detailed description of each bit is given in the stcf04 datasheet. when the status register is latched, reading and writing to the registers is still possible, but the bits flash_on and tch_on in the command register and auxl register cannot be changed until the device is unlatched. it is necessary to read the status register to unlatch the device. the atn pin is also pulled down when the internal timer reaches zero in flash mode. in this case the atn pin is pulled down for 11 s only. it is recommended to connect the atn pin to the interrupt input of the microcontroller. if it is not connected to the interrupt input, the atn pin should be polled fast enough so as not to miss the 11 s pulse; e.g., by a programming loop which is entered after starting flash mode. this loop runs until the atn pin gets low. it is recommended to make a timeout of such a loop. the atn pin is an open drain output and an external pull-up resistor should be connected to it. the atn pin is capable of sinking a maximum 3 ma current. this is why the minimum value of the pull-up resistor connected to it should not be lower than 1.8 k . table 11. status register bits bit name n/a f_run fl_r ntc_w ntc_h ot_f fl_ovr lth msb lsb table 12. effect of the status register bits on the operation of the device bit name f_run stat_reg fl_r stat_reg ntc_w stat_reg ntc_h stat_reg ot_f stat_reg fl_ovr stat_reg lth stat_reg default value 000 0 0 0 0 latched (1) no no yes yes yes no no forces ready mode when set no no no yes yes no no sets atn low when set no yes yes yes yes yes no 1. yes means that the bit is set by internal signals and is reset to its default value by an i2c read operation of stat_reg. no means that the bit is set and reset by internal signals in real-time.
ready pin AN3223 18/29 doc id 17553 rev 2 7 ready pin it is an open drain output, which provides information about the voltage on the super- capacitor. the signal is active low. the behavior of this pin depends on the mode of operation. 7.1 function of the ready pin in monitoring mode and torch mode (fixed) the threshold for the transition from high to low level is defined by the v dcthreshold voltage in this case. this voltage is set by the vdc_0 and vdc_1 bits in the feature register. the comparator works with a fixed hysteresis of 200 mv in this case, so the transition from low to high level occurs when the voltage of the super-capacitor falls to v dcthreshold - 0.2 v. 7.2 function of the ready pin in flash mode the threshold for the transition from high to low level is defined by the v dcthreshold voltage again. unlike monitoring mode, the transition from low to high occurs when the super-capacitor voltage falls to 4.2 v. this threshold is fixed and cannot be changed by any settings of the registers. figure 9. ready pin behavior in monitoring mode and torch mode (fixed) 200 mv v dcthre s hold ready pin level v s upercap 200 mv v dcthre s hold ready pin level v s upercap am07 8 0 3 v1
AN3223 ready pin doc id 17553 rev 2 19/29 7.3 function of the ready pin in torch mode (optimized) the threshold for the transition from high to low level is 4.2 v in this case. it is a fixed threshold, which cannot be changed by any settings of the registers. the transition from low to high occurs when the voltage on the ledin pin falls to 300 mv, which is the optimum value from an efficiency point of view. figure 10. ready pin behavior in flash mode ready pin level v dcthre s hold v s upercap 4.2 v ready pin level v dcthre s hold v s upercap 4.2 v am07 8 04v1 figure 11. ready pin behavior in torch mode optimized ready pin level v fwdled + 3 00 mv v s upercap 4.2 v ready pin level v fwdled + 3 00 mv v s upercap 4.2 v am07 8 05v1
ready pin AN3223 20/29 doc id 17553 rev 2 the ready pin is an open drain output, which is capable of sinking a maximum 3 ma current. that is why the minimum value of the pull-up resistor connected to it should not be lower than 1.8 k .
AN3223 the light sensor doc id 17553 rev 2 21/29 8 the light sensor the light sensor is an optional feature which optimizes the flash duration according to the light conditions in the flashed scene. this feature requires three external components to be connected to the stcf04 according to figure 12 . it is recommended to connect the collector of the phototransistor to v ref = 1.8 v. the integrating capacitor c int is discharged before every flash pulse. this reset takes approximately 200 s. during the flash the voltage on this capacitor increases according to the amount of light in the scene and t foto , r light , and c int parameters. the values of these components must be selected according to the final application purpose. figure 12. optional light sensor feature am07 8 06v1
reading and writing to the stcf04 registers through the i2c bus AN3223 22/29 doc id 17553 rev 2 9 reading and writing to the stcf04 registers through the i2c bus 9.1 writing to a single register writing to a single register starts with a start bit followed by the 7-bit device address of the stcf04. the 8 th bit is the r/w bit, which is 0 in this case. r/w = 1 means a reading operation. then the master awaits an acknowledgement from the stcf04. the 8-bit address of the desired register is sent afterwards to the stcf04. it is also followed by an acknowledge pulse. the last transmitted byte is the data which is going to be written into the register. it is followed again by an acknowledge pulse from stcf04. then the master generates a stop bit and the communication is over. see figure 13 below. 9.2 writing to multiple registers with incremental addressing it would not be practical to send the device address and the address of the register when writing to multiple registers several times. the stcf04 supports writing to multiple registers with incremental addressing. when data is written to a register, the register address is automatically incremented (by one), and therefore the next data can be sent without sending again the device address and the register address. see figure 14 below. figure 13. writing to a single register am07 8 07v1 s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter data a c k a c k s t o p m s b m s b l s b l s b s da line s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter data a c k a c k s t o p m s b m s b l s b l s b s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter data a c k a c k s t o p m s b m s b l s b l s b
AN3223 reading and writing to the stcf04 registers through the i2c bus doc id 17553 rev 2 23/29 9.3 reading from a single register the reading operation starts with a start bit followed by the 7-bit device address of the stcf04. the 8 th bit is the r/w-bit, which is 0 in this case. stcf04 confirms receipt of the address + r/w bit by an acknowledge pulse. the address of the register which should be read is sent and confirmed by an acknowledge pulse from the stcf04 again. then the master generates a start bit again and sends the device address followed by the r/w bit, which is now 1. the stcf04 confirms receipt of the address + r/w bit by an acknowledge pulse, and starts to send data to the master. no acknowledge pulse from the master is required after receiving the data. then, the master generates a stop bit to terminate the communication. see figure 15 below. 9.4 reading from multiple registers with incremental addressing reading from multiple registers starts in the same way as reading from a single register. as soon as the first register is read, the register address is automatically incremented. if the master generates an acknowledge pulse after receiving the data from the first register, then figure 14. writing to multiple register s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter i data i a c k a c k s t o p m s b m s b l s b l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n a c k m s b m s b m s b m s b m s b a c k l s b s da line s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter i data i a c k a c k s t o p m s b m s b l s b l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n a c k m s b m s b m s b m s b m s b a c k l s b s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w a c k addre ss of regi s ter i data i a c k a c k s t o p m s b m s b l s b l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n a c k m s b m s b m s b m s b m s b a c k l s b s da line am07 8 0 8 v1 figure 15. reading from a single register s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w addre ss of regi s ter a c k m s b l s b s t a r t a c k r / w r e a d device addre ss 7 bit s data l s b s t o p n o a c k s da line s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w addre ss of regi s ter a c k m s b l s b s t a r t a c k r / w r e a d device addre ss 7 bit s data l s b s t o p n o a c k s da line am07 8 09v1
reading and writing to the stcf04 registers through the i2c bus AN3223 24/29 doc id 17553 rev 2 reading from the next register can start immediately without having to once again send the device and the register addresses. the last acknowledge pulse before the stop-bit is not required. see figure 16 below. figure 16. reading from multiple registers am07 8 10v1 s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w addre ss of regi s ter i a c k m s b l s b s t a r t a c k r / w r e a d device addre ss 7 bit s data i a c k s t o p l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n m s b m s b m s b m s b a c k l s b n o a c k s da line s t a r t device addre ss 7 bit s a c k w r i t e m s b l s b r / w addre ss of regi s ter i a c k m s b l s b s t a r t a c k r / w r e a d device addre ss 7 bit s data i a c k s t o p l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n m s b m s b m s b m s b a c k l s b n o a c k s da line
AN3223 examples of register setup for each mode doc id 17553 rev 2 25/29 10 examples of register setup for each mode 10.1 example 1: 10 a flash with 30 ms duration the value of fdim (3 bits) must be set to 0x7. the value of ftim (5 bits) must be set to 0x6. bit pwr_on must be set to 1. bit flash_on must be set to 1. bit tch_on must be set to 0. bit ntc_on can be set to any value, because ntc is automatically on when flash mode is active. setting this bit to 0 does not switch off the ntc. it is necessary to write 4 bytes to the stcf04 to make a flash. 10.2 example 2: 60 ma torch with 10 s duration the value of tdim (4 bits) must be set to 0x4 to setup the current source to 60 ma. bit pwr_on must be set to 1. bit flash_on must be set to 0. bit tch_on must be set to 1. bit ntc_on can be set to any value, because ntc is automatically on, when torch mode is active. setting this bit to 0 does not switch off the ntc. table 13. command register data for entering flash mode cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 1 1 000000 msb lsb table 14. flash register data fl_reg ftim_4 ftim_3 ftim_2 ftim_1 ftim_0 fdim_2 fdim_1 fdim_0 00110111 msb lsb table 15. i2c data packet for activation of flash mode byte hex binary comment 1 62 01100000device address + r/w bit 2 00 00000000command register address 3 c1 11000000data of the command register 4 37 00110111data of the flash register
examples of register setup for each mode AN3223 26/29 doc id 17553 rev 2 the following packet sets the torch register. the following packet sets the command register. the torch pin must be high to enter torch mode. 10.3 example 3: an auxiliary led running at 10 ma for 500 ms the auxiliary led can be activated from idle mode only. a 10 ma output current is reached when auxi is set to 0x2. auxt must be set to 0x5 to have 500 ms duration of the auxiliary led lighting. table 16. command register data for entering torch mode cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 1 0 100000 msb lsb table 17. torch register data dim_reg ttrch1 ttrch0 tdim_3 tdim_2 tdim_1 tdim_0 n/a n/a 10010000 msb lsb table 18. i2c data packet for setting the torch register byte hex binary comment 1 60 01100000 device address + r/w bit 2 05 00000101 to rch register address 3 90 10010000 data of the to rch register table 19. i2c data packet for setting the command register byte hex binary comment 1 60 01100000 device address + r/w-bit 2 00 00000000 command register address 3 a0 10100000 data of the command register
AN3223 examples of register setup for each mode doc id 17553 rev 2 27/29 writing the 3 bytes in ta b l e 2 2 to stcf04 puts it into idle mode. this can be skipped if it is already in idle mode. writing the following 3 bytes to the stcf04 activates the auxiliary led for the desired time. table 20. command register data for the aux_led cmd_reg pwr_on flash_on tch_on ntc_on tchv_h chrg montr n/a 1 0 000000 msb lsb table 21. aux_led register data aux_led auxi_3 auxi_2 auxi_1 auxi_0 auxt_3 auxt_2 auxt_1 auxt_0 00100101 msb lsb table 22. i2c data packet for activating idle mode byte hex binary comment 1 60 01100000 device address + r/w bit 2 00 00000000 command register address 3 80 10000000 data of the command register table 23. i2c data packet for activating the aux_led byte hex binary comment 1 60 01100000 device address + r/w bit 2 02 00000010 auxiliary led register address 3 25 00100101 data of the auxiliary led register
revision history AN3223 28/29 doc id 17553 rev 2 11 revision history table 24. document revision history date revision changes 27-aug-2010 1 initial release. 13-feb-2012 2 modified title in cover page. removed references to part number stcs44.
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